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Kolanchinathan, V.P.
- Design and Implementation of the Combinational Circuits Testing using Accumulator based BIST to Reduce Delay, Power Consumption and Area
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1 St. Peter’s University, Chennai - 600109, Tamil Nadu, IN
2 Department of ECE, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai - 600062, Tamil Nadu, IN
1 St. Peter’s University, Chennai - 600109, Tamil Nadu, IN
2 Department of ECE, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai - 600062, Tamil Nadu, IN